1. Field of the Invention
This invention relates to hybrid electromechanical and semiconductor memory arrays and, in particular, to hybrid electromechanical and semiconductor configuration bit arrays often used in programmable logic devices.
2. History of the Prior Art
Memory structures are an essential building block for electronics devices and systems. There are a number of different types of memory structures which display differing characteristics making them suitable for different applications. One specialized application for memories is to program interconnections in a field programmable gate array (FPGA). A field programmable gate array is an integrated circuit that includes a two-dimensional array of general-purpose logic circuits whose functions are programmable. The logic circuits are linked to one another by programmable buses. Memory cells can be used to program the interconnect buses to select among a variety of different functions that the logic circuits are able to perform. A field programmable gate array is described in U.S. Pat. No. 6,531,891.
Prior art user programmable switches in a FPGA have been implemented in various technologies including static random access memory (SRAM) cells, flash electrically programmable read only memory (EPROM) cells, and electrically erasable programmable read only memory (EEPROM) cells. Memory cells that serve the purpose of configuring user programmable switches in a FPGA are referred to as “configuration bits.”
Recently, the authors of “Carbon Nanotube-Based Nonvolatile Random Access Memory for Molecular Computing,” Science, vol. 289, pp. 94-97, Jul. 7, 2000, proposed memory devices which use nanoscopic wires, such as single-walled carbon nanotubes, to form crossbar junctions which could serve as memory cells. The article describes individual single-walled nanotube wires suspended over other wires to define memory cells. In one condition, the wires do not touch and, thus, form an open circuit junction in a circuit adapted to transfer signals. However, electrical potentials may be furnished to the wires to cause them to physically attract one another and form a rectified junction. Each physical state (i.e., attracted or open) corresponds to an electrical state. When electric power is removed from the junction, the wires retain their physical (and thus electrical) state thereby forming a non-volatile memory cell. The carbon nanotube memory cell device described in the article is referred to hereinafter as an electromechanical device.
U.S. Pat. No. 6,574,130, entitled “Hybrid Circuit Having Nanotube Electromechanical Memory,” Segal et al, furnishes additional details including modifications for manufacturability of such memory devices.
As the patent discloses, not only may a single carbon nanotube be utilized to construct such switches, but a layer of nanotube mesh, a layer of densely-packed carbon nanotubes, or some similar flexible conductive nanoscopic material may also be utilized. Furthermore, the patent teaches that it is possible to construct a hybrid electromechanical technology memory cell using semiconductor and carbon nanotube technology.
Carbon nanotube memory cell devices offer a number of advantages not provided by prior art memory cells. They are small, fast, and non-volatile. It is desirable to utilize carbon nanotube memory cell devices to provide the configuration bits in field programmable gate arrays.